1. Field of the Invention
The present invention relates to a data communication control device having an uncompetitive bus construction which enables high-speed data communication.
2. Description of the Prior Art
A data communication control device for controlling data transmission between a network bus NB and a system bus SB of a host processor is well known.
Before an explanation on the data communication control device of the prior art, the role of the data communication control device in the entire body of a system is described.
As shown in FIG. 1, the system includes a host processor 100, a data communication control device 200 connected between a system bus SB connected to the host processor 100 and a network bus NB, a read-only memory (ROM) 300 in which is stored a data communication procedure for controlling the data communication control device 200, a random access memory (RAM) 400 for containing data to be transmitted and received through the system bus SB, and a terminal 500 connected to the network bus NB. In the transmission mode, data contained in the RAM 400 are transmitted to the network bus NB from the system bus SB by the data communication control device 200. While, in the reception mode, data derived from the terminal 500 are received in the RAM 400 through the system bus SB from the network bus NB by the data communication control device 200. Namely, according to the above construction, transmission control of data is carried out between the system bus SB and the network bus NB by the data communication control device 200.
Next, a construction of a data communication control device according to the prior art will be explained with reference to FIG. 2.
As shown in FIG. 2, the data communication control device is composed of a network bus interface (NBI) 10, a microprocessor 20 for controlling data transmission, a control logic circuit portion 30, a two-port memory 40 for holding transmission data, a direct memory access (DMA) portion 50 for carrying out access of the two-port memory, a system bus interface (SBI) 60 and a switch 70. Incidentally, reference character NB shows a network bus and SB shows a system bus of a host processor. Moreover, a port 1 of the two-port memory 40, a buffer 2 of the SBI 60 and the microprocessor 20 are connected by a data bus B.sub.3, and a port 2 of the two-port memory 40 and the switch 70 are connected by a data bus B.sub.4, further the switch 70 and NBI 10 and DMA 50 are respectively connected by data buses B.sub.1 and B.sub.2. In the system, the switch 70 is switched under control of the control logic circuit portion 30 to alternately connect the data buses B.sub.1, B.sub.2 to the data bus B.sub.4 connected to the port 2 of the two-port memory 40.
Next, operation of the data communication control device of the prior art with the construction as mentioned above will be described.
First, the transmission mode from the system bus SB to the network bus NB is explained.
When a command of data transmission is transmitted to the data communication control device from the host processor 100 through the system bus SB, the command is transmitted to the buffer 2 of the SBI 60, then is given to the microprocessor 20 through the data bus B.sub.3.
Then, transmission data are transmitted to the buffer 1 of the SBI 60 from the RAM 400 through the system bus SB, then are given to the switch 70 through the DMA 50 and the data bus B.sub.2. At the same time, a part of the transmission data from the RAM 400 are given to the buffer 2 of the system bus interface (SBI) 60, then transmitted to the port 1 of the two-port memory 40 through the data bus B.sub.3. The switch 70 is switched in accordance with control of the microprocessor 20 which received the transmission command and the control logic circuit portion 30 so as to connect the data bus B.sub.2 and the data bus B.sub.4, then the transmission data are inputted to the port 2 of the two-port memory 40 through the data bus B.sub.4. Thereafter, the two-port memory 40 changes or arranges the transmission data in accordance with control of the microprocessor 20 and the control logic circuit portion 30, and a part of the transmission data arranged and the transmission data transmitted to the port 1 are transmitted to the switch 70 through the data bus B.sub.4. Then, the switch 70 is switched under control of the microprocessor 20 and the control logic circuit portion 30 so as to connect the data bus B.sub.4 and the data bus B.sub.1, and the transmission data are transmitted to the network bus NB through the data bus B.sub.1 and the NBI 10.
Next, the reception mode of data from the network bus NB to the system bus SB is described.
First, a command of data reception is transmitted to the buffer 2 of the SBI 60 from the host processor 100 through the system bus SB, and given to the microprocessor 20 through the data bus B.sub.3. Then, reception data are transmitted to the NBI 10 from the terminal 500 through the network bus NB, thereafter given to the switch 70 through the data bus B.sub.1. The switch 70 is switched under control of the microprocessor 20 which received the reception command and the control logic circuit portion 30 so as to connect the data bus B.sub.1 and the data bus B.sub.4. Thereafter, the reception data are inputted to the port 2 of the two-port memory 40 through the data bus B.sub.4. Then, the two-port memory 40 changes or arranges the reception data in accordance with control of the microprocessor 20 and the control logic circuit portion 30, and the reception data arranged are transmitted to the switch 70 through the data bus B.sub.4 from the port 2. The switch 70 is switched under control of the microprocessor 20 and the control logic circuit portion 30 so as to connect the data bus B.sub.4 and the data bus B.sub.2, and the reception data are transmitted to the system bus SB through the data bus B.sub.2, DMA 50 and SBI 60.
However, in the data communication control device according to the prior art as shown in FIG. 2, the switch 70 is provided on the side of the port 2 in the two-port memory 40 so as to switch the data buses B.sub.1 and B.sub.2 under control of the control logic circuit portion 30 on each transmission or reception of data. Accordingly, elevation of the operational speed of the switch 70 is so limited that it is difficult to realize high-speed data transmission.
Moreover, since the buffer 2 of the SBI 60, the microprocessor 20 and the port 1 of the two-port memory 40 are connected by the one line of data bus B.sub.3, competition on use of the data bus B.sub.3 is caused between the port 1 of the two-port memory 40, microprocessor 20 and SBI 60. Thus, the operation of the microprocessor 20 is restricted.
For example, in the transmission mode, the command from the system bus SB is transmitted to the microprocessor 20 through the system bus interface (SBI) 60 and the data bus B.sub.3 as well as a part of the transmission data from the system bus SB are transmitted to the port 1 of the two-port memory 40 through the system bus interface (SBI) 60 and the data bus B.sub.3. Accordingly, the utilization rate or factor of the data bus B.sub.3 is very high.
As the result, it is difficult to carry out high-speed data transmission or high-speed data communication in the data communication control device according to the prior art, which has a bus construction for switching the connection between the port 2 of the two-port memory 40 and the data bus B.sub.1 or B.sub.2 through the switch 70 and causing the competition on use of the data bus B.sub.3 on the side of the port 1 in the memory 40.